1. Field of the Invention
The present invention relates to microprocessors employing pipelined architecture for executing and processing instructions, and particularly to microprocessors which can suppress a disturbance occurring in the pipelined architecture to effectively improve performance of the microprocessors.
2. Description of Prior Art
In recent years, microprocessors tend to employ the pipelined architecture in executing and processing instructions to improve performance of the microprocessors. Pipelined architecture generally comprises the stages of instruction fetch, instruction decode, effective address calculation address conversion, operand read, instruction execution and operand write, as described in "The Whole Picture of 32-Bit Microprocessors, Enterprises, Strategy, Technology and Market Trends," NIKKEI-McGRAW-HILL, INC., pp. 137 to 139.
In this sort of pipelined architecture, a high-function instruction "Im" having a memory operand will be processed in the effective address calculation stage to calculate an effective address of the instruction Im and in the address conversion stage to convert the effective address into a physical address. However, these address calculation and conversion stages are not necessary for a basic instruction "IR" having no memory operand.
FIG. 12 shows flows of a sequence of instructions Im, IR, Im, IR, Im and IR which are pipeline-processed. In figure, it is assumed that a process of each pipeline stage is completed in a single cycle and that an operand write process of each high-function instruction Im is carried out with respect to a register and completed in the execution stage. A mark "x" indicates that a corresponding stage in a corresponding cycle is idle in operation.
As apparent in FIG. 12, the effective address calculation stage is idle in cycles 4 and 6, and the address conversion stage is idle in cycles 5 and 7. Namely, an operating ratio of each of these two stages is 50%.
A complex instruction set computer (CISC) type microprocessor employs sets of complex high-function instructions "Ic" each requiring several cycles in its execution stage.
FIG. 13 shows flows of a sequence of instructions Ic, IR, IR, IR and Im which are pipeline-processed in the CISC type microprocessor. In this figure, the instruction Ic needs four cycles in the execution stage. A mark "x" in FIG. 13 indicates that a corresponding stage in a corresponding cycle is idle in operation.
As is apparent in FIG. 13, the instruction Ic requiring four cycles in execution causes a so-called "pipeline disturbance." Due to this, execution of all the instructions is not completed in an ideal pipeline flow represented with a hatched portion in FIG. 13, but the execution needs additional three cycles (cycles 12 to 14) more than the ideal flow.
Since the instruction Ic needs four cycles for executing the same, idling occurs in the stages of effective address calculation, address conversion and operand read.
The disturbance will not occur if the high-function instructions Im each having a memory operand and the basic instructions IR having no memory operand are alternately executed. However, even with no pipeline disturbance, the microprocessor may suffer from deterioration of operating ratios in the effective address calculation and address conversion stages, as shown in FIG. 12.
When the complex high-function instructions Ic each requiring several cycles in execution are involved, the pipeline disturbance unavoidably occurs to deteriorate performance of the microprocessor, in addition to the operating ratio deterioration occurring in the above-mentioned stages.